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wdt.h

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01	1 Copyright (c) 2002, 2004 Marek Michalkiewicz
	022Copyright (c) 2005, 2006, 2007 Eric B. Weddington
033All rights reserved. 044 055Redistribution and use in source and binary forms, with or without 066modification, are permitted provided that the following conditions are met: 077 088* Redistributions of source code must retain the above copyright 099notice, this list of conditions and the following disclaimer. 1010 1111* Redistributions in binary form must reproduce the above copyright 1212notice, this list of conditions and the following disclaimer in 1313the documentation and/or other materials provided with the 1414distribution. 1515 1616* Neither the name of the copyright holders nor the names of 1717contributors may be used to endorse or promote products derived 1818from this software without specific prior written permission. 1919 2020THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 2121AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2222IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2323ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 2424LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2525CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2626SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2727INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2828CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2929ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3030POSSIBILITY OF SUCH DAMAGE. */ 3131 3232/* $Id: wdt.h 2503 2016-02-07 22:59:47Z joerg_wunsch $ */ 3333 3434/* 3535avr/wdt.h - macros for AVR watchdog timer 3636*/ 3737 3838#ifndef _AVR_WDT_H_ 3939#define _AVR_WDT_H_ 4040 4141#include <avr/io.h> 4242#include <stdint.h> 4343 4444/** \file */ 4545/** \defgroup avr_watchdog <avr/wdt.h>: Watchdog timer handling 4646\code #include <avr/wdt.h> \endcode 4747 4848This header file declares the interface to some inline macros 4949handling the watchdog timer present in many AVR devices. In order 5050to prevent the watchdog timer configuration from being 5151accidentally altered by a crashing application, a special timed 5252sequence is required in order to change it. The macros within 5353this header file handle the required sequence automatically 5454before changing any value. Interrupts will be disabled during 5555the manipulation. 5656 5757\note Depending on the fuse configuration of the particular 5858device, further restrictions might apply, in particular it might 5959be disallowed to turn off the watchdog timer. 6060 6161Note that for newer devices (ATmega88 and newer, effectively any 6262AVR that has the option to also generate interrupts), the watchdog 6363timer remains active even after a system reset (except a power-on 6464condition), using the fastest prescaler value (approximately 15 6565ms). It is therefore required to turn off the watchdog early 6666during program startup, the datasheet recommends a sequence like 6767the following: 6868 6969\code 7070#include <stdint.h> 7171#include <avr/wdt.h> 7272 7373uint8_t mcusr_mirror __attribute__ ((section (".noinit"))); 7474 7575void get_mcusr(void) \ 7676__attribute__((naked)) \ 7777__attribute__((section(".init3"))); 7878void get_mcusr(void) 7979{ 8080mcusr_mirror = MCUSR; 8181MCUSR = 0; 8282wdt_disable(); 8383} 8484\endcode 8585 8686Saving the value of MCUSR in \c mcusr_mirror is only needed if the 8787application later wants to examine the reset source, but in particular, 8888clearing the watchdog reset flag before disabling the 8989watchdog is required, according to the datasheet. 9090*/ 9191 9292/** 9393\ingroup avr_watchdog 9494Reset the watchdog timer. When the watchdog timer is enabled, 9595a call to this instruction is required before the timer expires, 9696otherwise a watchdog-initiated device reset will occur. 9797*/ 9898 99 99#define wdt_reset() __asm__ __volatile__ ("wdr") 100100 101101#ifndef __DOXYGEN__ 102102 103103#if defined(WDP3) 104104# define _WD_PS3_MASK _BV(WDP3) 105105#else 106106# define _WD_PS3_MASK 0x00 107107#endif 108108 109109#if defined(WDTCSR) 110110# define _WD_CONTROL_REG WDTCSR 111111#elif defined(WDTCR) 112112# define _WD_CONTROL_REG WDTCR 113113#else 114114# define _WD_CONTROL_REG WDT 115115#endif 116116 117117#if defined(WDTOE) 118118#define _WD_CHANGE_BIT WDTOE 119119#else 120120#define _WD_CHANGE_BIT WDCE 121121#endif 122122 123123#endif /* !__DOXYGEN__ */ 124124 125125 126126/** 127127\ingroup avr_watchdog 128128Enable the watchdog timer, configuring it for expiry after 129129\c timeout (which is a combination of the \c WDP0 through 130130\c WDP2 bits to write into the \c WDTCR register; For those devices 131131that have a \c WDTCSR register, it uses the combination of the \c WDP0 132132through \c WDP3 bits). 133133 134134See also the symbolic constants \c WDTO_15MS et al. 135135*/ 136136 137137 138138#if defined(__AVR_XMEGA__) 139139 140140/* 141141wdt_enable(timeout) for xmega devices 142142** write signature (CCP_IOREG_gc) that enables change of protected I/O 143143registers to the CCP register 144144** At the same time, 1451451) set WDT change enable (WDT_CEN_bm) 1461462) enable WDT (WDT_ENABLE_bm) 1471473) set timeout (timeout) 148148** Synchronization starts when ENABLE bit of WDT is set. So, wait till it 149149finishes (SYNCBUSY of STATUS register is automatically cleared after the 150150sync is finished). 151151*/ 152152#define wdt_enable(timeout) \ 153153 do { \ 154154 uint8_t temp; \ 155155__asm__ __volatile__ ( \ 156156"in __tmp_reg__, %[rampd]" "\n\t" \ 157157"out %[rampd], __zero_reg__" "\n\t" \ 158158"out %[ccp_reg], %[ioreg_cen_mask]" "\n\t" \ 159159"sts %[wdt_reg], %[wdt_enable_timeout]" "\n\t" \ 160160"1:lds %[tmp], %[wdt_status_reg]" "\n\t" \ 161161"sbrc %[tmp], %[wdt_syncbusy_bit]" "\n\t" \ 162162"rjmp 1b" "\n\t" \ 163163"out %[rampd], __tmp_reg__" "\n\t" \ 164164: [tmp] "=r" (temp) \ 165165: [rampd] "I" (_SFR_IO_ADDR(RAMPD)), \ 166166[ccp_reg] "I" (_SFR_IO_ADDR(CCP)), \ 167167[ioreg_cen_mask] "r" ((uint8_t)CCP_IOREG_gc), \ 168168[wdt_reg] "n" (_SFR_MEM_ADDR(WDT_CTRL)), \ 169169[wdt_enable_timeout] "r" ((uint8_t)(WDT_CEN_bm | WDT_ENABLE_bm | timeout)), \ 170170[wdt_status_reg] "n" (_SFR_MEM_ADDR(WDT_STATUS)), \ 171171[wdt_syncbusy_bit] "I" (WDT_SYNCBUSY_bm) \ 172172: "r0" \ 173173); \ 174174} while(0) 175175 176176#define wdt_disable() \ 177177__asm__ __volatile__ ( \ 178178"in __tmp_reg__, %[rampd]" "\n\t" \ 179179"out %[rampd], __zero_reg__" "\n\t" \ 180180"out %[ccp_reg], %[ioreg_cen_mask]" "\n\t" \ 181181"sts %[wdt_reg], %[disable_mask]" "\n\t" \ 182182"out %[rampd], __tmp_reg__" "\n\t" \ 183183: \ 184184: [rampd] "I" (_SFR_IO_ADDR(RAMPD)), \ 185185[ccp_reg] "I" (_SFR_IO_ADDR(CCP)), \ 186186[ioreg_cen_mask] "r" ((uint8_t)CCP_IOREG_gc), \ 187187[wdt_reg] "n" (_SFR_MEM_ADDR(WDT_CTRL)), \ 188188[disable_mask] "r" ((uint8_t)((~WDT_ENABLE_bm) | WDT_CEN_bm)) \ 189189: "r0" \ 190190); 191191 192192#elif defined(__AVR_TINY__) 193193 194194#define wdt_enable(value) \ 195195__asm__ __volatile__ ( \ 196196"in __tmp_reg__,__SREG__" "\n\t" \ 197197"cli" "\n\t" \ 198198"wdr" "\n\t" \ 199199"out %[CCPADDRESS],%[SIGNATURE]" "\n\t" \ 200200"out %[WDTREG],%[WDVALUE]" "\n\t" \ 201201"out __SREG__,__tmp_reg__" "\n\t" \ 202202: /* no outputs */ \ 203203: [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)), \ 204204[SIGNATURE] "r" ((uint8_t)0xD8), \ 205205[WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \ 206206[WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00) \ 207207| _BV(WDE) | (value & 0x07) )) \ 208208: "r16" \ 209209) 210210 211211#define wdt_disable() \ 212212 do { \ 213213 uint8_t temp_wd; \ 214214__asm__ __volatile__ ( \ 215215"in __tmp_reg__,__SREG__" "\n\t" \ 216216"cli" "\n\t" \ 217217"wdr" "\n\t" \ 218218"out %[CCPADDRESS],%[SIGNATURE]" "\n\t" \ 219219"in %[TEMP_WD],%[WDTREG]" "\n\t" \ 220220"cbr %[TEMP_WD],%[WDVALUE]" "\n\t" \ 221221"out %[WDTREG],%[TEMP_WD]" "\n\t" \ 222222"out __SREG__,__tmp_reg__" "\n\t" \ 223223: /*no output */ \ 224224: [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)), \ 225225[SIGNATURE] "r" ((uint8_t)0xD8), \ 226226[WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \ 227227[TEMP_WD] "d" (temp_wd), \ 228228[WDVALUE] "n" (1 << WDE) \ 229229: "r16" \ 230230); \ 231231}while(0) 232232 233233#elif defined(CCP) 234234 235235static __inline__ 236236__attribute__ ((__always_inline__)) 237237 void wdt_enable (const uint8_t value) 238238{ 239239if (!_SFR_IO_REG_P (CCP) && !_SFR_IO_REG_P (_WD_CONTROL_REG)) 240240{ 241241__asm__ __volatile__ ( 242242"in __tmp_reg__,__SREG__" "\n\t" 243243"cli" "\n\t" 244244"wdr" "\n\t" 245245"sts %[CCPADDRESS],%[SIGNATURE]" "\n\t" 246246"sts %[WDTREG],%[WDVALUE]" "\n\t" 247247"out __SREG__,__tmp_reg__" "\n\t" 248248: /* no outputs */ 249249: [CCPADDRESS] "n" (_SFR_MEM_ADDR(CCP)), 250250[SIGNATURE] "r" ((uint8_t)0xD8), 251251[WDTREG] "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), 252252[WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00) 253253| _BV(WDE) | (value & 0x07) )) 254254: "r0" 255255); 256256} 257257else if (!_SFR_IO_REG_P (CCP) && _SFR_IO_REG_P (_WD_CONTROL_REG)) 258258{ 259259__asm__ __volatile__ ( 260260"in __tmp_reg__,__SREG__" "\n\t" 261261"cli" "\n\t" 262262"wdr" "\n\t" 263263"sts %[CCPADDRESS],%[SIGNATURE]" "\n\t" 264264"out %[WDTREG],%[WDVALUE]" "\n\t" 265265"out __SREG__,__tmp_reg__" "\n\t" 266266: /* no outputs */ 267267: [CCPADDRESS] "n" (_SFR_MEM_ADDR(CCP)), 268268[SIGNATURE] "r" ((uint8_t)0xD8), 269269[WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), 270270[WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00) 271271| _BV(WDE) | (value & 0x07) )) 272272: "r0" 273273); 274274} 275275else if (_SFR_IO_REG_P (CCP) && !_SFR_IO_REG_P (_WD_CONTROL_REG)) 276276{ 277277__asm__ __volatile__ ( 278278"in __tmp_reg__,__SREG__" "\n\t" 279279"cli" "\n\t" 280280"wdr" "\n\t" 281281"out %[CCPADDRESS],%[SIGNATURE]" "\n\t" 282282"sts %[WDTREG],%[WDVALUE]" "\n\t" 283283"out __SREG__,__tmp_reg__" "\n\t" 284284: /* no outputs */ 285285: [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)), 286286[SIGNATURE] "r" ((uint8_t)0xD8), 287287[WDTREG] "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), 288288[WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00) 289289| _BV(WDE) | (value & 0x07) )) 290290: "r0" 291291); 292292} 293293else 294294{ 295295__asm__ __volatile__ ( 296296"in __tmp_reg__,__SREG__" "\n\t" 297297"cli" "\n\t" 298298"wdr" "\n\t" 299299"out %[CCPADDRESS],%[SIGNATURE]" "\n\t" 300300"out %[WDTREG],%[WDVALUE]" "\n\t" 301301"out __SREG__,__tmp_reg__" "\n\t" 302302: /* no outputs */ 303303: [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)), 304304[SIGNATURE] "r" ((uint8_t)0xD8), 305305[WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), 306306[WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00) 307307| _BV(WDE) | (value & 0x07) )) 308308: "r0" 309309); 310310} 311311} 312312 313313static __inline__ 314314__attribute__ ((__always_inline__)) 315315 void wdt_disable (void) 316316{ 317317if (!_SFR_IO_REG_P (CCP) && !_SFR_IO_REG_P(_WD_CONTROL_REG)) 318318{ 319319uint8_t temp_wd; 320320__asm__ __volatile__ ( 321321"in __tmp_reg__,__SREG__" "\n\t" 322322"cli" "\n\t" 323323"wdr" "\n\t" 324324"sts %[CCPADDRESS],%[SIGNATURE]" "\n\t" 325325"lds %[TEMP_WD],%[WDTREG]" "\n\t" 326326"cbr %[TEMP_WD],%[WDVALUE]" "\n\t" 327327"sts %[WDTREG],%[TEMP_WD]" "\n\t" 328328"out __SREG__,__tmp_reg__" "\n\t" 329329: /*no output */ 330330: [CCPADDRESS] "n" (_SFR_MEM_ADDR(CCP)), 331331[SIGNATURE] "r" ((uint8_t)0xD8), 332332[WDTREG] "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), 333333[TEMP_WD] "d" (temp_wd), 334334[WDVALUE] "n" (1 << WDE) 335335: "r0" 336336); 337337} 338338else if (!_SFR_IO_REG_P (CCP) && _SFR_IO_REG_P(_WD_CONTROL_REG)) 339339{ 340340uint8_t temp_wd; 341341__asm__ __volatile__ ( 342342"in __tmp_reg__,__SREG__" "\n\t" 343343"cli" "\n\t" 344344"wdr" "\n\t" 345345"sts %[CCPADDRESS],%[SIGNATURE]" "\n\t" 346346"in %[TEMP_WD],%[WDTREG]" "\n\t" 347347"cbr %[TEMP_WD],%[WDVALUE]" "\n\t" 348348"out %[WDTREG],%[TEMP_WD]" "\n\t" 349349"out __SREG__,__tmp_reg__" "\n\t" 350350: /*no output */ 351351: [CCPADDRESS] "n" (_SFR_MEM_ADDR(CCP)), 352352[SIGNATURE] "r" ((uint8_t)0xD8), 353353[WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), 354354[TEMP_WD] "d" (temp_wd), 355355[WDVALUE] "n" (1 << WDE) 356356: "r0" 357357); 358358} 359359else if (_SFR_IO_REG_P (CCP) && !_SFR_IO_REG_P(_WD_CONTROL_REG)) 360360{ 361361uint8_t temp_wd; 362362__asm__ __volatile__ ( 363363"in __tmp_reg__,__SREG__" "\n\t" 364364"cli" "\n\t" 365365"wdr" "\n\t" 366366"out %[CCPADDRESS],%[SIGNATURE]" "\n\t" 367367"lds %[TEMP_WD],%[WDTREG]" "\n\t" 368368"cbr %[TEMP_WD],%[WDVALUE]" "\n\t" 369369"sts %[WDTREG],%[TEMP_WD]" "\n\t" 370370"out __SREG__,__tmp_reg__" "\n\t" 371371: /*no output */ 372372: [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)), 373373[SIGNATURE] "r" ((uint8_t)0xD8), 374374[WDTREG] "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), 375375[TEMP_WD] "d" (temp_wd), 376376[WDVALUE] "n" (1 << WDE) 377377: "r0" 378378); 379379} 380380else 381381{ 382382uint8_t temp_wd; 383383__asm__ __volatile__ ( 384384"in __tmp_reg__,__SREG__" "\n\t" 385385"cli" "\n\t" 386386"wdr" "\n\t" 387387"out %[CCPADDRESS],%[SIGNATURE]" "\n\t" 388388"in %[TEMP_WD],%[WDTREG]" "\n\t" 389389"cbr %[TEMP_WD],%[WDVALUE]" "\n\t" 390390"out %[WDTREG],%[TEMP_WD]" "\n\t" 391391"out __SREG__,__tmp_reg__" "\n\t" 392392: /*no output */ 393393: [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)), 394394[SIGNATURE] "r" ((uint8_t)0xD8), 395395[WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), 396396[TEMP_WD] "d" (temp_wd), 397397[WDVALUE] "n" (1 << WDE) 398398: "r0" 399399); 400400} 401401} 402402 403403#else 404404 405405static __inline__ 406 406 __attribute__ ((__always_inline__)) 407407 void wdt_enable (const uint8_t value) 408408{ 409409if (_SFR_IO_REG_P (_WD_CONTROL_REG)) 410410{ 411411__asm__ __volatile__ ( 412412"in __tmp_reg__,__SREG__" "\n\t" 413413"cli" "\n\t" 414414"wdr" "\n\t" 415415"out %0, %1" "\n\t" 416416"out __SREG__,__tmp_reg__" "\n\t" 417417"out %0, %2" "\n \t" 418418: /* no outputs */ 419419: "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), 420420"r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))), 421421"r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) | 422422_BV(WDE) | (value & 0x07)) ) 423423: "r0" 424424); 425425} 426426else 427427{ 428428__asm__ __volatile__ ( 429429"in __tmp_reg__,__SREG__" "\n\t" 430430"cli" "\n\t" 431431"wdr" "\n\t" 432432"sts %0, %1" "\n\t" 433433"out __SREG__,__tmp_reg__" "\n\t" 434434"sts %0, %2" "\n \t" 435435: /* no outputs */ 436436: "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), 437437"r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))), 438438"r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) | 439439_BV(WDE) | (value & 0x07)) ) 440440: "r0" 441441); 442442} 443443} 444444 445445static __inline__ 446446__attribute__ ((__always_inline__)) 447447 void wdt_disable (void) 448448{ 449449if (_SFR_IO_REG_P (_WD_CONTROL_REG)) 450450{ 451451uint8_t register temp_reg; 452452__asm__ __volatile__ ( 453453"in __tmp_reg__,__SREG__" "\n\t" 454454"cli" "\n\t" 455455"wdr" "\n\t" 456456"in %[TEMPREG],%[WDTREG]" "\n\t" 457457"ori %[TEMPREG],%[WDCE_WDE]" "\n\t" 458458"out %[WDTREG],%[TEMPREG]" "\n\t" 459459"out %[WDTREG],__zero_reg__" "\n\t" 460460"out __SREG__,__tmp_reg__" "\n\t" 461461: [TEMPREG] "=d" (temp_reg) 462462: [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), 463463[WDCE_WDE] "n" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))) 464464: "r0" 465465); 466466} 467467else 468468{ 469469uint8_t register temp_reg; 470470__asm__ __volatile__ ( 471471"in __tmp_reg__,__SREG__" "\n\t" 472472"cli" "\n\t" 473473"wdr" "\n\t" 474474"lds %[TEMPREG],%[WDTREG]" "\n\t" 475475"ori %[TEMPREG],%[WDCE_WDE]" "\n\t" 476476"sts %[WDTREG],%[TEMPREG]" "\n\t" 477477"sts %[WDTREG],__zero_reg__" "\n\t" 478478"out __SREG__,__tmp_reg__" "\n\t" 479479: [TEMPREG] "=d" (temp_reg) 480480: [WDTREG] "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), 481481[WDCE_WDE] "n" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))) 482482: "r0" 483483); 484484} 485485} 486486 487487#endif 488488 489489 490490/** 491491\ingroup avr_watchdog 492492Symbolic constants for the watchdog timeout. Since the watchdog 493493timer is based on a free-running RC oscillator, the times are 494494approximate only and apply to a supply voltage of 5 V. At lower 495495supply voltages, the times will increase. For older devices, the 496496times will be as large as three times when operating at Vcc = 3 V, 497497while the newer devices (e. g. ATmega128, ATmega8) only experience 498498a negligible change. 499499 500500Possible timeout values are: 15 ms, 30 ms, 60 ms, 120 ms, 250 ms, 501501500 ms, 1 s, 2 s. (Some devices also allow for 4 s and 8 s.) 502502Symbolic constants are formed by the prefix 503503\c WDTO_, followed by the time. 504504 505505Example that would select a watchdog timer expiry of approximately 506506500 ms: 507507\code 508508wdt_enable(WDTO_500MS); 509509\endcode 510510*/ 511 511#define WDTO_15MS 0 512512 513513/** \ingroup avr_watchdog 514514See \c WDTO_15MS */ 515 515#define WDTO_30MS 1 516516 517517/** \ingroup avr_watchdog 518518See \c WDTO_15MS */ 519 519#define WDTO_60MS 2 520520 521521/** \ingroup avr_watchdog 522522See \c WDTO_15MS */ 523 523#define WDTO_120MS 3 524524 525525/** \ingroup avr_watchdog 526526See \c WDTO_15MS */ 527 527#define WDTO_250MS 4 528528 529529/** \ingroup avr_watchdog 530530See \c WDTO_15MS */ 531 531#define WDTO_500MS 5 532532 533533/** \ingroup avr_watchdog 534534See \c WDTO_15MS */ 535 535#define WDTO_1S 6 536536 537537/** \ingroup avr_watchdog 538538See \c WDTO_15MS */ 539 539#define WDTO_2S 7 540540 541541#if defined(__DOXYGEN__) || defined(WDP3) 542542 543543/** \ingroup avr_watchdog 544544See \c WDTO_15MS 545545Note: This is only available on the 546546ATtiny2313, 547547ATtiny24, ATtiny44, ATtiny84, ATtiny84A, 548548ATtiny25, ATtiny45, ATtiny85, 549549ATtiny261, ATtiny461, ATtiny861, 550550ATmega48, ATmega88, ATmega168, 551551ATmega48P, ATmega88P, ATmega168P, ATmega328P, 552552ATmega164P, ATmega324P, ATmega644P, ATmega644, 553553ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, 554554ATmega8HVA, ATmega16HVA, ATmega32HVB, 555555ATmega406, ATmega1284P, 556556AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, 557557AT90PWM81, AT90PWM161, 558558AT90USB82, AT90USB162, 559559AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, 560560ATtiny48, ATtiny88. 561561*/ 562 562#define WDTO_4S 8 563563 564564/** \ingroup avr_watchdog 565565See \c WDTO_15MS 566566Note: This is only available on the 567567ATtiny2313, 568568ATtiny24, ATtiny44, ATtiny84, ATtiny84A, 569569ATtiny25, ATtiny45, ATtiny85, 570570ATtiny261, ATtiny461, ATtiny861, 571571ATmega48, ATmega48A, ATmega48PA, ATmega88, ATmega168, 572572ATmega48P, ATmega88P, ATmega168P, ATmega328P, 573573ATmega164P, ATmega324P, ATmega644P, ATmega644, 574574ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, 575575ATmega8HVA, ATmega16HVA, ATmega32HVB, 576576ATmega406, ATmega1284P, 577577ATmega2564RFR2, ATmega256RFR2, ATmega1284RFR2, ATmega128RFR2, ATmega644RFR2, ATmega64RFR2 578578AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, 579579AT90PWM81, AT90PWM161, 580580AT90USB82, AT90USB162, 581581AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, 582582ATtiny48, ATtiny88, 583583ATxmega16a4u, ATxmega32a4u, 584584ATxmega16c4, ATxmega32c4, 585585ATxmega128c3, ATxmega192c3, ATxmega256c3. 586586*/ 587 587#define WDTO_8S 9 588588 589589#endif /* defined(__DOXYGEN__) || defined(WDP3) */ 590590591591 592592#endif /* _AVR_WDT_H_ */

io.h

uint8_t unsigned char uint8_t

Definition: stdint.h:83

_BV #define _BV(bit)

Definition: sfr_defs.h:208

stdint.h

__attribute__ static __inline__ __attribute__((__always_inline__)) void wdt_enable(const uint8_t value)

Definition: wdt.h:406