022* ----------------------------------------------------------------------------
033* "THE BEER-WARE LICENSE" (Revision 42):
044* <joerg@FreeBSD.ORG> wrote this file. As long as you retain this notice you
055* can do whatever you want with this stuff. If we meet some day, and you think
066* this stuff is worth it, you can buy me a beer in return. Joerg Wunsch
077* ----------------------------------------------------------------------------
088*
099* IO feature compatibility definitions for various AVRs.
1010*
1111* $Id: iocompat.h 2384 2013-05-03 12:38:46Z joerg_wunsch $
1212*/
1313
1414#if !defined(IOCOMPAT_H)
1515#define IOCOMPAT_H 1
1616
1717/*
1818* Device-specific adjustments:
1919*
2020* Supply definitions for the location of the OCR1[A] port/pin, the
2121* name of the OCR register controlling the PWM, and adjust interrupt
2222* vector names that differ from the one used in demo.c
2323* [TIMER1_OVF_vect].
2424*/
2525#if defined(__AVR_AT90S2313__)
2626# define OC1 PB3
2727# define OCR OCR1
2828# define DDROC DDRB
2929# define TIMER1_OVF_vect TIMER1_OVF1_vect
3030#elif defined(__AVR_AT90S2333__) || defined(__AVR_AT90S4433__)
3131# define OC1 PB1
3232# define DDROC DDRB
3333# define OCR OCR1
3434#elif defined(__AVR_AT90S4414__) || defined(__AVR_AT90S8515__) || \
3535defined(__AVR_AT90S4434__) || defined(__AVR_AT90S8535__) || \
3636defined(__AVR_ATmega163__) || defined(__AVR_ATmega8515__) || \
3737defined(__AVR_ATmega8535__) || \
3838defined(__AVR_ATmega164P__) || defined(__AVR_ATmega324P__) || \
3939defined(__AVR_ATmega644__) || defined(__AVR_ATmega644P__) || \
4040defined(__AVR_ATmega1284P__)
4141# define OC1 PD5
4242# define DDROC DDRD
4343# define OCR OCR1A
4444# if !defined(TIMSK) /* new ATmegas */
4545# define TIMSK TIMSK1
4646# endif
4747#elif defined(__AVR_ATmega8__) || defined(__AVR_ATmega48__) || \
4848defined(__AVR_ATmega88__) || defined(__AVR_ATmega168__)
4949# define OC1 PB1
5050# define DDROC DDRB
5151# define OCR OCR1A
5252# if !defined(TIMSK) /* ATmega48/88/168 */
5353# define TIMSK TIMSK1
5454# endif /* !defined(TIMSK) */
5555#elif defined(__AVR_ATtiny2313__)
5656# define OC1 PB3
5757# define OCR OCR1A
5858# define DDROC DDRB
5959#elif defined(__AVR_ATtiny24__) || defined(__AVR_ATtiny44__) || \
6060defined(__AVR_ATtiny84__)
6161# define OC1 PA6
6262# define DDROC DDRA
6363# if !defined(OCR1A)
6464# /* work around misspelled name in avr-libc 1.4.[0..1] */
6565# define OCR OCRA1
6666# else
6767# define OCR OCR1A
6868# endif
6969# define TIMSK TIMSK1
7070# define TIMER1_OVF_vect TIM1_OVF_vect /* XML and datasheet mismatch */
7171#elif defined(__AVR_ATtiny25__) || defined(__AVR_ATtiny45__) || \
7272defined(__AVR_ATtiny85__)
7373/* Timer 1 is only an 8-bit timer on these devices. */
7474# define OC1 PB1
7575# define DDROC DDRB
7676# define OCR OCR1A
7777# define TCCR1A TCCR1
7878# define TCCR1B TCCR1
7979# define TIMER1_OVF_vect TIM1_OVF_vect
8080# define TIMER1_TOP 255 /* only 8-bit PWM possible */
8181# define TIMER1_PWM_INIT _BV(PWM1A) | _BV(COM1A1)
8282# define TIMER1_CLOCKSOURCE _BV(CS12) /* use 1/8 prescaler */
8383#elif defined(__AVR_ATtiny26__)
8484/* Rather close to ATtinyX5 but different enough for its own section. */
8585# define OC1 PB1
8686# define DDROC DDRB
8787# define OCR OCR1A
8888# define TIMER1_OVF_vect TIMER1_OVF1_vect
8989# define TIMER1_TOP 255 /* only 8-bit PWM possible */
9090# define TIMER1_PWM_INIT _BV(PWM1A) | _BV(COM1A1)
9191# define TIMER1_CLOCKSOURCE _BV(CS12) /* use 1/8 prescaler */
9292/*
9393* Without setting OCR1C to TOP, the ATtiny26 does not trigger an
9494* overflow interrupt in PWM mode.
9595*/
9696# define TIMER1_SETUP_HOOK() OCR1C = 255
9797#elif defined(__AVR_ATtiny261__) || defined(__AVR_ATtiny461__) || \
9898defined(__AVR_ATtiny861__)
9999# define OC1 PB1
100100# define DDROC DDRB
101101# define OCR OCR1A
102102# define TIMER1_PWM_INIT _BV(WGM10) | _BV(PWM1A) | _BV(COM1A1)
103103/*
104104* While timer 1 could be operated in 10-bit mode on these devices,
105105* the handling of the 10-bit IO registers is more complicated than
106106* that of the 16-bit registers of other AVR devices (no combined
107107* 16-bit IO operations possible), so we restrict this demo to 8-bit
108108* mode which is pretty standard.
109109*/
110110# define TIMER1_TOP 255
111111# define TIMER1_CLOCKSOURCE _BV(CS12) /* use 1/8 prescaler */
112112#elif defined(__AVR_ATmega32__) || defined(__AVR_ATmega16__)
113113# define OC1 PD5
114114# define DDROC DDRD
115115# define OCR OCR1A
116116#elif defined(__AVR_ATmega64__) || defined(__AVR_ATmega128__) || \
117117defined(__AVR_ATmega165__) || defined(__AVR_ATmega169__) || \
118118defined(__AVR_ATmega325__) || defined(__AVR_ATmega3250__) || \
119119defined(__AVR_ATmega645__) || defined(__AVR_ATmega6450__) || \
120120defined(__AVR_ATmega329__) || defined(__AVR_ATmega3290__) || \
121121defined(__AVR_ATmega649__) || defined(__AVR_ATmega6490__) || \
122122defined(__AVR_ATmega640__) || \
123123defined(__AVR_ATmega1280__) || defined(__AVR_ATmega1281__) || \
124124defined(__AVR_ATmega2560__) || defined(__AVR_ATmega2561__) || \
125125defined(__AVR_ATmega32U4__)
126126# define OC1 PB5
127127# define DDROC DDRB
128128# define OCR OCR1A
129129# if !defined(PB5) /* work around missing bit definition */
130130# define PB5 5
131131# endif
132132# if !defined(TIMSK) /* new ATmegas */
133133# define TIMSK TIMSK1
134134# endif
135135#else
136136# error "Don't know what kind of MCU you are compiling for"
137137#endif
138138
139139/*
140140* Map register names for older AVRs here.
141141*/
142142#if !defined(COM1A1)
143143# define COM1A1 COM11
144144#endif
145145
146146#if !defined(WGM10)
147147# define WGM10 PWM10
148148# define WGM11 PWM11
149149#endif
150150
151151/*
152152* Provide defaults for device-specific macros unless overridden
153153* above.
154154*/
155155#if !defined(TIMER1_TOP)
156156# define TIMER1_TOP 1023 /* 10-bit PWM */
157157#endif
158158
159159#if !defined(TIMER1_PWM_INIT)
160160# define TIMER1_PWM_INIT _BV(WGM10) | _BV(WGM11) | _BV(COM1A1)
161161#endif
162162
163163#if !defined(TIMER1_CLOCKSOURCE)
164164# define TIMER1_CLOCKSOURCE _BV(CS10) /* full clock */
165165#endif
166166
167167#endif /* !defined(IOCOMPAT_H) */
