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boot.8h
Go to the documentation of this file.01 1 Copyright (c) 2002,2003,2004,2005,2006,2007,2008,2009 Eric B. Weddington02 2All rights reserved. 03 3 04 4Redistribution and use in source and binary forms, with or without 05 5modification, are permitted provided that the following conditions are met: 06 607 7* Redistributions of source code must retain the above copyright 08 8notice, this list of conditions and the following disclaimer. 09 9* Redistributions in binary form must reproduce the above copyright 10 10notice, this list of conditions and the following disclaimer in 11 11the documentation and/or other materials provided with the 12 12distribution. 13 13* Neither the name of the copyright holders nor the names of 14 14contributors may be used to endorse or promote products derived 15 15from this software without specific prior written permission. 16 1617 17THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 18AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 19IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 20ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21 21LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 22CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 23SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 24INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 25CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 26ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 27POSSIBILITY OF SUCH DAMAGE. */ 28 2829 29/* $Id: boot.h 2503 2016-02-07 22:59:47Z joerg_wunsch $ */ 30 3031 31#ifndef _AVR_BOOT_H_ 32 32#define _AVR_BOOT_H_ 1 33 3334 34/** \file */ 35 35/** \defgroup avr_boot <avr/boot.h>: Bootloader Support Utilities 36 36\code 37 37#include <avr/io.h> 38 38#include <avr/boot.h> 39 39\endcode 40 4041 41The macros in this module provide a C language interface to the 42 42bootloader support functionality of certain AVR processors. These 43 43macros are designed to work with all sizes of flash memory. 44 4445 45Global interrupts are not automatically disabled for these macros. It 46 46is left up to the programmer to do this. See the code example below. 47 47Also see the processor datasheet for caveats on having global interrupts 48 48enabled during writing of the Flash. 49 4950 50\note Not all AVR processors provide bootloader support. See your 51 51processor datasheet to see if it provides bootloader support. 52 5253 53\todo From email with Marek: On smaller devices (all except ATmega64/128), 54 54__SPM_REG is in the I/O space, accessible with the shorter "in" and "out" 55 55instructions - since the boot loader has a limited size, this could be an 56 56important optimization. 57 5758 58\par API Usage Example 59 59The following code shows typical usage of the boot API. 60 6061 61\code 62 62#include <inttypes.h> 63 63#include <avr/interrupt.h> 64 64#include <avr/pgmspace.h> 65 6566 66void boot_program_page (uint32_t page, uint8_t *buf) 67 67{ 68 68uint16_t i; 69 69uint8_t sreg; 70 7071 71// Disable interrupts. 72 7273 73sreg = SREG; 74 74cli(); 75 7576 76eeprom_busy_wait (); 77 7778 78boot_page_erase (page); 79 79boot_spm_busy_wait (); // Wait until the memory is erased. 80 8081 81for (i=0; i<SPM_PAGESIZE; i+=2) 82 82{ 83 83// Set up little-endian word. 84 8485 85uint16_t w = *buf++; 86 86w += (*buf++) << 8; 87 8788 88boot_page_fill (page + i, w); 89 89} 90 9091 91boot_page_write (page); // Store buffer in flash page. 92 92boot_spm_busy_wait(); // Wait until the memory is written. 93 9394 94// Reenable RWW-section again. We need this if we want to jump back 95 95// to the application after bootloading. 96 9697 97boot_rww_enable (); 98 9899 99// Re-enable interrupts (if they were ever enabled). 100 100101 101SREG = sreg; 102 102}\endcode */ 103 103104 104#include <avr/eeprom.h> 105 105#include <avr/io.h> 106 106#include <inttypes.h> 107 107#include <limits.h> 108 108109 109/* Check for SPM Control Register in processor. */ 110 110#if defined (SPMCSR) 111 111# define __SPM_REG SPMCSR 112 112#else 113 113# if defined (SPMCR) 114 114# define __SPM_REG SPMCR 115 115# else 116 116# error AVR processor does not provide bootloader support! 117 117# endif 118 118#endif 119 119120 120121 121/* Check for SPM Enable bit. */ 122 122#if defined(SPMEN) 123 123# define __SPM_ENABLE SPMEN 124 124#elif defined(SELFPRGEN) 125 125# define __SPM_ENABLE SELFPRGEN 126 126#else 127 127# error Cannot find SPM Enable bit definition! 128 128#endif 129 129130 130/** \ingroup avr_boot 131 131\def BOOTLOADER_SECTION 132 132133 133Used to declare a function or variable to be placed into a 134 134new section called .bootloader. This section and its contents 135 135can then be relocated to any address (such as the bootloader 136 136NRWW area) at link-time. */ 137 137138 138#define BOOTLOADER_SECTION __attribute__ ((section (".bootloader"))) 139 139140 140#ifndef __DOXYGEN__ 141 141/* Create common bit definitions. */ 142 142#ifdef ASB 143 143#define __COMMON_ASB ASB 144 144#else 145 145#define __COMMON_ASB RWWSB 146 146#endif 147 147148 148#ifdef ASRE 149 149#define __COMMON_ASRE ASRE 150 150#else 151 151#define __COMMON_ASRE RWWSRE 152 152#endif 153 153154 154/* Define the bit positions of the Boot Lock Bits. */ 155 155156 156#define BLB12 5 157 157#define BLB11 4 158 158#define BLB02 3 159 159#define BLB01 2 160 160#endif /* __DOXYGEN__ */ 161 161162 162/** \ingroup avr_boot 163 163\def boot_spm_interrupt_enable() 164 164Enable the SPM interrupt. */ 165 165166 166#define boot_spm_interrupt_enable() (__SPM_REG |= (uint8_t)_BV(SPMIE)) 167 167168 168/** \ingroup avr_boot 169 169\def boot_spm_interrupt_disable() 170 170Disable the SPM interrupt. */ 171 171172 172#define boot_spm_interrupt_disable() (__SPM_REG &= (uint8_t)~_BV(SPMIE)) 173 173174 174/** \ingroup avr_boot 175 175\def boot_is_spm_interrupt() 176 176Check if the SPM interrupt is enabled. */ 177 177178 178#define boot_is_spm_interrupt() (__SPM_REG & (uint8_t)_BV(SPMIE)) 179 179180 180/** \ingroup avr_boot 181 181\def boot_rww_busy() 182 182Check if the RWW section is busy. */ 183 183184 184#define boot_rww_busy() (__SPM_REG & (uint8_t)_BV(__COMMON_ASB)) 185 185186 186/** \ingroup avr_boot 187 187\def boot_spm_busy() 188 188Check if the SPM instruction is busy. */ 189 189190 190#define boot_spm_busy() (__SPM_REG & (uint8_t)_BV(__SPM_ENABLE)) 191 191192 192/** \ingroup avr_boot 193 193\def boot_spm_busy_wait() 194 194Wait while the SPM instruction is busy. */ 195 195196 196#define boot_spm_busy_wait() do{}while(boot_spm_busy()) 197 197198 198#ifndef __DOXYGEN__ 199 199#define __BOOT_PAGE_ERASE (_BV(__SPM_ENABLE) | _BV(PGERS)) 200 200#define __BOOT_PAGE_WRITE (_BV(__SPM_ENABLE) | _BV(PGWRT)) 201 201#define __BOOT_PAGE_FILL _BV(__SPM_ENABLE) 202 202#define __BOOT_RWW_ENABLE (_BV(__SPM_ENABLE) | _BV(__COMMON_ASRE)) 203 203#if defined(BLBSET) 204 204#define __BOOT_LOCK_BITS_SET (_BV(__SPM_ENABLE) | _BV(BLBSET)) 205 205#elif defined(RFLB) /* Some devices have RFLB defined instead of BLBSET. */ 206 206#define __BOOT_LOCK_BITS_SET (_BV(__SPM_ENABLE) | _BV(RFLB)) 207 207#endif 208 208209 209#define __boot_page_fill_normal(address, data) \ 210 210(__extension__({ \ 211 211__asm__ __volatile__ \ 212 212( \ 213 213"movw r0, %3\n\t" \ 214 214"sts %0, %1\n\t" \ 215 215"spm\n\t" \ 216 216"clr r1\n\t" \ 217 217: \ 218 218: "i" (_SFR_MEM_ADDR(__SPM_REG)), \ 219 219"r" ((uint8_t)(__BOOT_PAGE_FILL)), \ 220 220"z" ((uint16_t)(address)), \ 221 221"r" ((uint16_t)(data)) \ 222 222: "r0" \ 223 223); \ 224 224})) 225 225226 226#define __boot_page_fill_alternate(address, data)\ 227 227(__extension__({ \ 228 228__asm__ __volatile__ \ 229 229( \ 230 230"movw r0, %3\n\t" \ 231 231"sts %0, %1\n\t" \ 232 232"spm\n\t" \ 233 233".word 0xffff\n\t" \ 234 234"nop\n\t" \ 235 235"clr r1\n\t" \ 236 236: \ 237 237: "i" (_SFR_MEM_ADDR(__SPM_REG)), \ 238 238"r" ((uint8_t)(__BOOT_PAGE_FILL)), \ 239 239"z" ((uint16_t)(address)), \ 240 240"r" ((uint16_t)(data)) \ 241 241: "r0" \ 242 242); \ 243 243})) 244 244245 245#define __boot_page_fill_extended(address, data) \ 246 246(__extension__({ \ 247 247__asm__ __volatile__ \ 248 248( \ 249 249"movw r0, %4\n\t" \ 250 250"movw r30, %A3\n\t" \ 251 251"sts %1, %C3\n\t" \ 252 252"sts %0, %2\n\t" \ 253 253"spm\n\t" \ 254 254"clr r1\n\t" \ 255 255: \ 256 256: "i" (_SFR_MEM_ADDR(__SPM_REG)), \ 257 257"i" (_SFR_MEM_ADDR(RAMPZ)), \ 258 258"r" ((uint8_t)(__BOOT_PAGE_FILL)), \ 259 259"r" ((uint32_t)(address)), \ 260 260"r" ((uint16_t)(data)) \ 261 261: "r0", "r30", "r31" \ 262 262); \ 263 263})) 264 264265 265#define __boot_page_erase_normal(address) \ 266 266(__extension__({ \ 267 267__asm__ __volatile__ \ 268 268( \ 269 269"sts %0, %1\n\t" \ 270 270"spm\n\t" \ 271 271: \ 272 272: "i" (_SFR_MEM_ADDR(__SPM_REG)), \ 273 273"r" ((uint8_t)(__BOOT_PAGE_ERASE)), \ 274 274"z" ((uint16_t)(address)) \ 275 275); \ 276 276})) 277 277278 278#define __boot_page_erase_alternate(address) \ 279 279(__extension__({ \ 280 280__asm__ __volatile__ \ 281 281( \ 282 282"sts %0, %1\n\t" \ 283 283"spm\n\t" \ 284 284".word 0xffff\n\t" \ 285 285"nop\n\t" \ 286 286: \ 287 287: "i" (_SFR_MEM_ADDR(__SPM_REG)), \ 288 288"r" ((uint8_t)(__BOOT_PAGE_ERASE)), \ 289 289"z" ((uint16_t)(address)) \ 290 290); \ 291 291})) 292 292293 293#define __boot_page_erase_extended(address) \ 294 294(__extension__({ \ 295 295__asm__ __volatile__ \ 296 296( \ 297 297"movw r30, %A3\n\t" \ 298 298"sts %1, %C3\n\t" \ 299 299"sts %0, %2\n\t" \ 300 300"spm\n\t" \ 301 301: \ 302 302: "i" (_SFR_MEM_ADDR(__SPM_REG)), \ 303 303"i" (_SFR_MEM_ADDR(RAMPZ)), \ 304 304"r" ((uint8_t)(__BOOT_PAGE_ERASE)), \ 305 305"r" ((uint32_t)(address)) \ 306 306: "r30", "r31" \ 307 307); \ 308 308})) 309 309310 310#define __boot_page_write_normal(address) \ 311 311(__extension__({ \ 312 312__asm__ __volatile__ \ 313 313( \ 314 314"sts %0, %1\n\t" \ 315 315"spm\n\t" \ 316 316: \ 317 317: "i" (_SFR_MEM_ADDR(__SPM_REG)), \ 318 318"r" ((uint8_t)(__BOOT_PAGE_WRITE)), \ 319 319"z" ((uint16_t)(address)) \ 320 320); \ 321 321})) 322 322323 323#define __boot_page_write_alternate(address) \ 324 324(__extension__({ \ 325 325__asm__ __volatile__ \ 326 326( \ 327 327"sts %0, %1\n\t" \ 328 328"spm\n\t" \ 329 329".word 0xffff\n\t" \ 330 330"nop\n\t" \ 331 331: \ 332 332: "i" (_SFR_MEM_ADDR(__SPM_REG)), \ 333 333"r" ((uint8_t)(__BOOT_PAGE_WRITE)), \ 334 334"z" ((uint16_t)(address)) \ 335 335); \ 336 336})) 337 337338 338#define __boot_page_write_extended(address) \ 339 339(__extension__({ \ 340 340__asm__ __volatile__ \ 341 341( \ 342 342"movw r30, %A3\n\t" \ 343 343"sts %1, %C3\n\t" \ 344 344"sts %0, %2\n\t" \ 345 345"spm\n\t" \ 346 346: \ 347 347: "i" (_SFR_MEM_ADDR(__SPM_REG)), \ 348 348"i" (_SFR_MEM_ADDR(RAMPZ)), \ 349 349"r" ((uint8_t)(__BOOT_PAGE_WRITE)), \ 350 350"r" ((uint32_t)(address)) \ 351 351: "r30", "r31" \ 352 352); \ 353 353})) 354 354355 355#define __boot_rww_enable() \ 356 356(__extension__({ \ 357 357__asm__ __volatile__ \ 358 358( \ 359 359"sts %0, %1\n\t" \ 360 360"spm\n\t" \ 361 361: \ 362 362: "i" (_SFR_MEM_ADDR(__SPM_REG)), \ 363 363"r" ((uint8_t)(__BOOT_RWW_ENABLE)) \ 364 364); \ 365 365})) 366 366367 367#define __boot_rww_enable_alternate() \ 368 368(__extension__({ \ 369 369__asm__ __volatile__ \ 370 370( \ 371 371"sts %0, %1\n\t" \ 372 372"spm\n\t" \ 373 373".word 0xffff\n\t" \ 374 374"nop\n\t" \ 375 375: \ 376 376: "i" (_SFR_MEM_ADDR(__SPM_REG)), \ 377 377"r" ((uint8_t)(__BOOT_RWW_ENABLE)) \ 378 378); \ 379 379})) 380 380381 381/* From the mega16/mega128 data sheets (maybe others): 382 382383 383Bits by SPM To set the Boot Loader Lock bits, write the desired data to 384 384R0, write "X0001001" to SPMCR and execute SPM within four clock cycles 385 385after writing SPMCR. The only accessible Lock bits are the Boot Lock bits 386 386that may prevent the Application and Boot Loader section from any 387 387software update by the MCU. 388 388389 389If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit 390 390will be programmed if an SPM instruction is executed within four cycles 391 391after BLBSET and SPMEN (or SELFPRGEN) are set in SPMCR. The Z-pointer is 392 392don't care during this operation, but for future compatibility it is 393 393recommended to load the Z-pointer with $0001 (same as used for reading the 394 394Lock bits). For future compatibility It is also recommended to set bits 7, 395 3956, 1, and 0 in R0 to 1 when writing the Lock bits. When programming the 396 396Lock bits the entire Flash can be read during the operation. */ 397 397398 398#define __boot_lock_bits_set(lock_bits) \ 399 399(__extension__({ \ 400 400uint8_t value = (uint8_t)(~(lock_bits)); \ 401 401__asm__ __volatile__ \ 402 402( \ 403 403"ldi r30, 1\n\t" \ 404 404"ldi r31, 0\n\t" \ 405 405"mov r0, %2\n\t" \ 406 406"sts %0, %1\n\t" \ 407 407"spm\n\t" \ 408 408: \ 409 409: "i" (_SFR_MEM_ADDR(__SPM_REG)), \ 410 410"r" ((uint8_t)(__BOOT_LOCK_BITS_SET)), \ 411 411"r" (value) \ 412 412: "r0", "r30", "r31" \ 413 413); \ 414 414})) 415 415416 416#define __boot_lock_bits_set_alternate(lock_bits) \ 417 417(__extension__({ \ 418 418uint8_t value = (uint8_t)(~(lock_bits)); \ 419 419__asm__ __volatile__ \ 420 420( \ 421 421"ldi r30, 1\n\t" \ 422 422"ldi r31, 0\n\t" \ 423 423"mov r0, %2\n\t" \ 424 424"sts %0, %1\n\t" \ 425 425"spm\n\t" \ 426 426".word 0xffff\n\t" \ 427 427"nop\n\t" \ 428 428: \ 429 429: "i" (_SFR_MEM_ADDR(__SPM_REG)), \ 430 430"r" ((uint8_t)(__BOOT_LOCK_BITS_SET)), \ 431 431"r" (value) \ 432 432: "r0", "r30", "r31" \ 433 433); \ 434 434})) 435 435#endif /* __DOXYGEN__ */ 436 436437 437/* 438 438Reading lock and fuse bits: 439 439440 440Similarly to writing the lock bits above, set BLBSET and SPMEN (or 441 441SELFPRGEN) bits in __SPMREG, and then (within four clock cycles) issue an 442 442LPM instruction. 443 443444 444Z address: contents: 445 4450x0000 low fuse bits 446 4460x0001 lock bits 447 4470x0002 extended fuse bits 448 4480x0003 high fuse bits 449 449450 450Sounds confusing, doesn't it? 451 451452 452Unlike the macros in pgmspace.h, no need to care for non-enhanced 453 453cores here as these old cores do not provide SPM support anyway. 454 454*/ 455 455456 456/** \ingroup avr_boot 457 457\def GET_LOW_FUSE_BITS 458 458address to read the low fuse bits, using boot_lock_fuse_bits_get 459 459*/ 460 460#define GET_LOW_FUSE_BITS (0x0000) 461 461/** \ingroup avr_boot 462 462\def GET_LOCK_BITS 463 463address to read the lock bits, using boot_lock_fuse_bits_get 464 464*/ 465 465#define GET_LOCK_BITS (0x0001) 466 466/** \ingroup avr_boot 467 467\def GET_EXTENDED_FUSE_BITS 468 468address to read the extended fuse bits, using boot_lock_fuse_bits_get 469 469*/ 470 470#define GET_EXTENDED_FUSE_BITS (0x0002) 471 471/** \ingroup avr_boot 472 472\def GET_HIGH_FUSE_BITS 473 473address to read the high fuse bits, using boot_lock_fuse_bits_get 474 474*/ 475 475#define GET_HIGH_FUSE_BITS (0x0003) 476 476477 477/** \ingroup avr_boot 478 478\def boot_lock_fuse_bits_get(address) 479 479480 480Read the lock or fuse bits at \c address. 481 481482 482Parameter \c address can be any of GET_LOW_FUSE_BITS, 483 483GET_LOCK_BITS, GET_EXTENDED_FUSE_BITS, or GET_HIGH_FUSE_BITS. 484 484485 485\note The lock and fuse bits returned are the physical values, 486 486i.e. a bit returned as 0 means the corresponding fuse or lock bit 487 487is programmed. 488 488*/ 489 489#define boot_lock_fuse_bits_get(address) \ 490 490(__extension__({ \ 491 491uint8_t __result; \ 492 492__asm__ __volatile__ \ 493 493( \ 494 494"sts %1, %2\n\t" \ 495 495"lpm %0, Z\n\t" \ 496 496: "=r" (__result) \ 497 497: "i" (_SFR_MEM_ADDR(__SPM_REG)), \ 498 498"r" ((uint8_t)(__BOOT_LOCK_BITS_SET)), \ 499 499"z" ((uint16_t)(address)) \ 500 500); \ 501 501__result; \ 502 502})) 503 503504 504#ifndef __DOXYGEN__ 505 505#define __BOOT_SIGROW_READ (_BV(__SPM_ENABLE) | _BV(SIGRD)) 506 506#endif 507 507/** \ingroup avr_boot 508 508\def boot_signature_byte_get(address) 509 509510 510Read the Signature Row byte at \c address. For some MCU types, 511 511this function can also retrieve the factory-stored oscillator 512 512calibration bytes. 513 513514 514Parameter \c address can be 0-0x1f as documented by the datasheet. 515 515\note The values are MCU type dependent. 516 516*/ 517 517518 518#define boot_signature_byte_get(addr) \ 519 519(__extension__({ \ 520 520uint8_t __result; \ 521 521__asm__ __volatile__ \ 522 522( \ 523 523"sts %1, %2\n\t" \ 524 524"lpm %0, Z" "\n\t" \ 525 525: "=r" (__result) \ 526 526: "i" (_SFR_MEM_ADDR(__SPM_REG)), \ 527 527"r" ((uint8_t)(__BOOT_SIGROW_READ)), \ 528 528"z" ((uint16_t)(addr)) \ 529 529); \ 530 530__result; \ 531 531})) 532 532533 533/** \ingroup avr_boot 534 534\def boot_page_fill(address, data) 535 535536 536Fill the bootloader temporary page buffer for flash 537 537address with data word. 538 538539 539\note The address is a byte address. The data is a word. The AVR 540 540writes data to the buffer a word at a time, but addresses the buffer 541 541per byte! So, increment your address by 2 between calls, and send 2 542 542data bytes in a word format! The LSB of the data is written to the lower 543 543address; the MSB of the data is written to the higher address.*/ 544 544545 545/** \ingroup avr_boot 546 546\def boot_page_erase(address) 547 547548 548Erase the flash page that contains address. 549 549550 550\note address is a byte address in flash, not a word address. */ 551 551552 552/** \ingroup avr_boot 553 553\def boot_page_write(address) 554 554555 555Write the bootloader temporary page buffer 556 556to flash page that contains address. 557 557558 558\note address is a byte address in flash, not a word address. */ 559 559560 560/** \ingroup avr_boot 561 561\def boot_rww_enable() 562 562563 563Enable the Read-While-Write memory section. */ 564 564565 565/** \ingroup avr_boot 566 566\def boot_lock_bits_set(lock_bits) 567 567568 568Set the bootloader lock bits. 569 569570 570\param lock_bits A mask of which Boot Loader Lock Bits to set. 571 571572 572\note In this context, a 'set bit' will be written to a zero value. 573 573Note also that only BLBxx bits can be programmed by this command. 574 574575 575For example, to disallow the SPM instruction from writing to the Boot 576 576Loader memory section of flash, you would use this macro as such: 577 577578 578\code 579 579boot_lock_bits_set (_BV (BLB11)); 580 580\endcode 581 581582 582\note Like any lock bits, the Boot Loader Lock Bits, once set, 583 583cannot be cleared again except by a chip erase which will in turn 584 584also erase the boot loader itself. */ 585 585586 586/* Normal versions of the macros use 16-bit addresses. 587 587Extended versions of the macros use 32-bit addresses. 588 588Alternate versions of the macros use 16-bit addresses and require special 589 589instruction sequences after LPM. 590 590591 591FLASHEND is defined in the ioXXXX.h file. 592 592USHRT_MAX is defined in <limits.h>. */ 593 593594 594#if defined(__AVR_ATmega161__) || defined(__AVR_ATmega163__) \ 595 595|| defined(__AVR_ATmega323__) 596 596597 597/* Alternate: ATmega161/163/323 and 16 bit address */ 598 598#define boot_page_fill(address, data) __boot_page_fill_alternate(address, data) 599 599#define boot_page_erase(address) __boot_page_erase_alternate(address) 600 600#define boot_page_write(address) __boot_page_write_alternate(address) 601 601#define boot_rww_enable() __boot_rww_enable_alternate() 602 602#define boot_lock_bits_set(lock_bits) __boot_lock_bits_set_alternate(lock_bits) 603 603604 604#elif (FLASHEND >> USHRT_MAX) 605 605606 606/* Extended: >16 bit address */ 607 607#define boot_page_fill(address, data) __boot_page_fill_extended(address, data) 608 608#define boot_page_erase(address) __boot_page_erase_extended(address) 609 609#define boot_page_write(address) __boot_page_write_extended(address) 610 610#define boot_rww_enable() __boot_rww_enable() 611 611#define boot_lock_bits_set(lock_bits) __boot_lock_bits_set(lock_bits) 612 612613 613#else 614 614615 615/* Normal: 16 bit address */ 616 616#define boot_page_fill(address, data) __boot_page_fill_normal(address, data) 617 617#define boot_page_erase(address) __boot_page_erase_normal(address) 618 618#define boot_page_write(address) __boot_page_write_normal(address) 619 619#define boot_rww_enable() __boot_rww_enable() 620 620#define boot_lock_bits_set(lock_bits) __boot_lock_bits_set(lock_bits) 621 621622 622#endif 623 623624 624/** \ingroup avr_boot 625 625626 626Same as boot_page_fill() except it waits for eeprom and spm operations to 627 627complete before filling the page. */ 628 628629 629#define boot_page_fill_safe(address, data) \ 630 630 do { \ 631 631boot_spm_busy_wait(); \ 632 632eeprom_busy_wait(); \ 633 633boot_page_fill(address, data); \ 634 634} while (0) 635 635636 636/** \ingroup avr_boot 637 637638 638Same as boot_page_erase() except it waits for eeprom and spm operations to 639 639complete before erasing the page. */ 640 640641 641#define boot_page_erase_safe(address) \ 642 642 do { \ 643 643boot_spm_busy_wait(); \ 644 644eeprom_busy_wait(); \ 645 645boot_page_erase (address); \ 646 646} while (0) 647 647648 648/** \ingroup avr_boot 649 649650 650Same as boot_page_write() except it waits for eeprom and spm operations to 651 651complete before writing the page. */ 652 652653 653#define boot_page_write_safe(address) \ 654 654 do { \ 655 655boot_spm_busy_wait(); \ 656 656eeprom_busy_wait(); \ 657 657boot_page_write (address); \ 658 658} while (0) 659 659660 660/** \ingroup avr_boot 661 661662 662Same as boot_rww_enable() except waits for eeprom and spm operations to 663 663complete before enabling the RWW mameory. */ 664 664665 665#define boot_rww_enable_safe() \ 666 666 do { \ 667 667boot_spm_busy_wait(); \ 668 668eeprom_busy_wait(); \ 669 669boot_rww_enable(); \ 670 670} while (0) 671 671672 672/** \ingroup avr_boot 673 673674 674Same as boot_lock_bits_set() except waits for eeprom and spm operations to 675 675complete before setting the lock bits. */ 676 676677 677#define boot_lock_bits_set_safe(lock_bits) \ 678 678 do { \ 679 679boot_spm_busy_wait(); \ 680 680eeprom_busy_wait(); \ 681 681boot_lock_bits_set (lock_bits); \ 682 682} while (0) 683 683684 684#endif /* _AVR_BOOT_H_ */